Semiconductor memory devices, including Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs), Electrically Erasable Programmable Read Only Memories (EEPROMs), and the like typically include an array of memory cells. The array of memory cells are arranged in rows and columns and store information in at least two states, for example, a logic high state (a logic “1” state) or a logic low state (a logic “0” state). To access this state information, a unique address is employed. The address is based on row/column locations and is decoded by address decode circuitry, which identifies the particular row and column of the memory array.
In manufacturing such memories, it is found that some of the memory cells can be defective. To repair these defective memory cells, memory devices provide redundant blocks of memory cells that can be used to replace, for example, an entire row of memory cells in which the defective cells are located. Often, only a minority of memory cells in a row are found to be defective. There is a need in the art for an efficient way of repairing memory cells.